The present invention relates to a semiconductor integrated circuit device, a method of testing a semiconductor integrated circuit device and a method of manufacturing a semiconductor integrated circuit device. More particularly, the present invention concerns an effective technique for use in a technique for determining a write failure and a precharge failure in a high-speed operating dynamic random access memory (RAM) configured as a semiconductor integrated circuit device, by using a low-speed testing apparatus, for example.
A dynamic RAM configured as a semiconductor integrated circuit device is tested by application of an appropriate operation control signal and a data signal and by reference to output data. In cases where it is necessary to confirm the operating speed of the dynamic RAM and where it is necessary to confirm an operation timing margin, testing is performed after periods of synchronization signals which are called a row address strobe (RAS) signal and a column address strobe (CAS) signal are appropriately set for testing. Namely, a period operation required for operation for selecting/nonselecting word lines in the RAM, amplifying operation of sense amplifiers, and precharging operation of bit lines, and the like vary according to variations in the fabrication of the RAM. Testing as to whether or not the variations of the period required for various appropriate operation fall within an allowable range becomes possible by the appropriately setting the synchronization signals.
Development of semiconductor integrated circuit device technologies in recent years has been remarkable, and increasingly highly sophisticated functions and higher-speed operation have been made possible. As for the dynamic RAMs as well, which are configured as semiconductor integrated circuit devices, those operating at a high speed at a frequency in the neighborhood of 100 MHz or below have become necessary and have been made available. Testing apparatus or testers which can be realistically used for practical purposes for the dynamic RAMs capable of high-speed operation of that kind operate at relatively low speeds with the clock operation of about 30 MHz.
Prior to the invention, the present inventors studied the possibility of high-speed testing of the RAM under the condition in which a low-speed testing apparatus is used. The technique of interest which was studied concerned a technique in which a portion of the internal timing control configuration of the memory is made shiftable from the configuration of responding to the normal level transition of a synchronization signal such as the RAS signal to the configuration of responding to the level transition in the opposite direction only during testing (i.e., a shift of the edge trigger is effected), and in which, during testing, the internal circuit of the memory is operated by a synchronization signal with an apparently short pulse width in combination with a pulse-width setting function or a pulse-duty ratio changing mechanism in a testing apparatus. In the case of a dynamic RAM whose operating speed is not very high such as 100 MHz or less, through the above-described studied technique, by using the aforementioned clock signal of about 30 MHz it becomes possible to conduct an evaluation of response characteristics of the internal circuit, i.e., those equivalent to a case in which the circuit is operated at the aforementioned 100 MHz, by the above-described control of the duty of the clock signal in the testing apparatus. That is, the evaluation of the high-speed operation of the RAM becomes possible.
According to this studied technique, however, the test of the dynamic RAMs for which even higher-speed operation is required becomes difficult. For example, in the case of a high-speed operating DRAM whose operating frequency is increased to about 400 MHz or thereabouts, the duty of the clock signal supplied from the above-described testing apparatus must be made extremely small, and the pulse duty becomes destroyed in a signal transmission path leading from the testing apparatus to the memory circuit, thereby making it impossible to reliably make an evaluation equivalent to that of a case in which the circuit is operated at the aforementioned 400 MHz or thereabouts. For this reason, the screening yield in the probing process declines, and wastes occur in the process ranging from assembly to screening with respect to the chips which essentially prove to be defective.
The difficulty of evaluation of the high-speed operating DRAM will be described below with reference to FIG. 12 illustrating an equivalent circuit of a memory cell portion and a sense amplifier portion of a DRAM. It should be noted that, in the high-speed operation of the dynamic RAM, effects due to variations of parasitic resistance which is present in the memory cell are unnegligible. Accordingly, in FIG. 12, the parasitic resistance which is generally not illustrated in drawings as it can be negligible is also illustrated. In the write cycle of the DRAM, a bit line (BL) in which two signals, a Y select signal (YS) and a write select signal (WS) are asserted is connected to a write I/O (WIO) to invert the bit line, and the bit line is made to undergo a full amplitude by the sense amplifier. Further, where a storage node of the memory cell has assumed the same potential as that of the bit line, the word line (WL) is made to fall to complete writing.
In the memory cell, as shown in the drawing, large parasitic resistances are present at a bit-line contact hole (BLCT) for connecting the bit line and a transfer MOSFET and a storage node contact hole (SNCT) for connecting a storage node and the transfer MOSFET, and faulty bits (memory cells) having even greater parasitic resistances are present in process variations. Therefore, unless these faulty bits are detected and remedied in a probing inspection (hereafter, P inspection), a decline in the screening yield after assembly results.
In addition, upon completion of writing, a precharge signal (PCH) is asserted, and the precharging of the bit line is effected in preparation for ensuing reading. Here, when the drive capability is weak due to the contact resistance of the precharging MOSFET and variations in Vth, its bit line fails to be fully precharged before the next read cycle, and the next word line is risen in a state in which the potential remains at the bit line. Hence, the amount of bit line signal which is read from the selected memory cell is destroyed, which acts an input offset for the sense amplifier, so that a read failure occurs. Unless such a bit line failure is remedied at the time of the P inspection, a decline in the screening yield after assembly results.
An object of the invention is to provide a semiconductor integrated circuit device which enables a high-speed operation test with high reliability by a simple configuration as well as a testing method therefor. Another object of the invention is to provide a method of manufacturing a semiconductor integrated circuit device which realizes the improvement of the screening yield by a simple configuration. The above and other objects and novel features of the invention will become more apparent from the description of the specification and the appended drawings.
In accordance with one aspect of the invention, there is provided a semiconductor integrated circuit device comprising: an internal circuit whose state of operation is controlled in response to an internal operation control signal; and a control circuit for forming the internal operation control signal, wherein the control circuit has its inputs connected to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal used exclusively for testing is supplied, the control circuit being capable of providing control between a test mode and a normal operation mode, wherein, in the test mode, the internal operation control signal is changed from a first state of control to a second state of control in response to a change of the external operation control signal from a first state to a second state, and the internal operation control signal is changed to the first state of control in response to the timing exclusively used for testing, and wherein, in the normal operation mode, the internal operation control signal is changed from the first state of control to the second state of control in response to the change of the external operation control signal from the first state to the second state, and the internal operation control signal is changed to the first state of control in response to the change of the external operation control signal to the first state.
In accordance with another aspect of the invention, there is provided a method of testing a memory circuit which has a plurality of signal nodes to which an operation control signal for controlling memory selecting operation and an operation timing signal are supplied, and in which word-line selecting operation, sense amplifier operation following the word-line selecting operation, memory selecting operation including data transmitting operation, and the termination of the memory selecting operation including the termination of the word-line selecting operation are effected on the basis of the operation control signal, a reference timing of the internal operation of the memory circuit being set by the operation timing signal, comprising the steps of: setting a frequency of the timing signal at the time of test operation by a testing apparatus to a level lower than that at the time of normal memory operation in correspondence with the performance of the testing apparatus; and changing a period of operation by the operation control signal by combining the timing signal at the time of the test operation with a timing signal used exclusively for testing so as to test response characteristics of the memory circuit.
In accordance with still another aspect of the invention, there is provided a method of manufacturing a memory circuit which has a plurality of signal nodes to which an operation control signal for controlling memory selecting operation and an operation timing signal are supplied, and in which word-line selecting operation, sense amplifier operation following the word-line selecting operation, memory selecting operation including data transmitting operation, and the termination of the memory selecting operation including the termination of the word-line selecting operation are effected on the basis of the operation control signal, a reference timing of the internal operation of the memory circuit being set by the operation timing signal, the memory circuit having a defect remedy circuit, comprising: a first step of preparing a semiconductor integrated circuit substrate on which the memory circuit and the defect remedy circuit are formed; a second step of testing response characteristics of the memory circuit by a testing apparatus by setting a frequency of the timing signal to a level lower than that at the time of normal operation in correspondence with the performance of the testing apparatus, by controlling a period of operation of the memory circuit through a combination of the timing signal and a timing signal used exclusively for testing, and by controlling the period of operation; a third step of determining a portion of the memory circuit whose defect is to be remedied on the basis of a result of the testing of the response characteristics; and a fourth step of remedying by the defect remedy circuit the portion whose defect is to be remedied and which has been determined in the third step.